Conference paper
Circuit implications of gate oxide breakdown
J.H. Stathis, R. Rodríguez, et al.
Microelectronics Reliability
Trapped holes are shown to induce]] slow" interface states by their presence that are distinctly different from other types of interface states. These slow states can be alternately introduced and removed by sequential hole generation and annihilation. Various experiments and techniques are used to rule out explanations involving artifacts due to lateral nonuniformities in the hole trapping. © 1995 American Institute of Physics.
J.H. Stathis, R. Rodríguez, et al.
Microelectronics Reliability
B.P. Linder, J.H. Stathis, et al.
IRPS 2001
J.H. Stathis, A. Vayshenker, et al.
VLSI Technology 2000
J.H. Stathis
Applied Physics Letters