Publication
IEEE JSSC
Paper

Model for a 15 ns 16K RAM with Josephson Junctions

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Abstract

An experimental memory model for investigating the feasibility of a 16K RAM memory with Josephson junctions was fabricated and tested. There are nearly 4500 Josephson junctions in the design which includes array, line drivers, and address decoders. Storage element is a single flux-quantum (SFQ) cell arranged in a 2K array. Drivers and decoders are based on the principle of current steering in superconducting loops, which is a medium speed but low power approach. The measured read-access time of the model is approximately 10 ns. Power dissipation of the unselected chip is zero, whereas for a read/write cycle time of 30 ns, it amounts to about 10 µW. Results indicate that a 16K chip is feasible electrically. The estimated access time and power dissipation are 15ns and 40 µW, respectively. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1979

Publication

IEEE JSSC