Substrate noise coupling in 3-D CMOS SOI technology is characterized using hardware measurement. Couplings between device contacts and through-silicon vias (TSVs) are measured in frequency domain. Time domain simulations based on the measured S-parameters are performed to assess the impact of TSV-induced noise coupling on active circuit performance. Equivalent circuits are constructed with good model-to-hardware correlation. The characterization results demonstrate a dominant noise-coupling path through N+ epi layer in the SOI substrate. The data also successfully validates our proposed noise mitigation technique of using CMOS process compatible buried interface contacts, e.g., achieving over 20-dB reduction for TSV-induced substrate noise coupling at 1 GHz. © 2013 IEEE.