Materials Design of Phase Change Memory for Analog In- Memory Computing Applications

Abstract

The increasing size and complexity of AI models present a significant challenge to traditional Von-Neumann computing architectures, which require frequent data transfers between memory and compute elements. This creates a bottleneck known as the "memory wall" [1]. To overcome this challenge, innovative approaches such as in-memory computing (IMC) are being explored, where computations are performed directly within the memory. IMC has the potential to offer dramatic improvements in speed and energy efficiency. Analog AI accelerators can leverage IMC to eliminate resource-intensive data shuffling, resulting in enhanced computational efficiency. One promising technology for enabling this new compute paradigm is phase-change memory (PCM) [2]. However, PCM exhibits inherent imperfections that can introduce errors and reduce the accuracy of Deep Neural Network (DNN) computations. A major issue is the intrinsic structural relaxation in amorphous phase, causing resistance drift. Moreover, drift and its variability are dependent on conductance levels, posing significant challenges to maintaining compute precision. In this talk, we will provide an overview of the material properties and device performance required for analog AI applications. We will show the evaluation of SiSbTe-based phase-change memory (PCM) devices, focusing on two crucial metrics for IMC applications: resistance drift and data retention. The absolute value of resistance drift and its dependence on resistance levels are both critical factors. However, PCM materials with low resistance drift coefficient (n) often exhibit poor data retention, presenting a trade-off between drift and retention when selecting optimized materials. We will then present the results where we simulate PCM as analog weight elements for matrix-vector multiplication operations in BERT deep neural networks (DNNs) using the SQuAD dataset, employing the IBM Analog Hardware Acceleration Kit (AIHWKit) [3, 4]. Different drift vs. conductance profiles is designed to understand the importance of state-independent drift characteristic. The fabricated SiSbTe PCM devices maintain BERT accuracy for over 7 days at 65°C and demonstrate successful data retention at 85°C for 48 hours, showcasing a well-balanced performance between the two metrics. 1. https://medium.com/riselab/ai-and-memory-wall-2cb4265cb0b8. 2. G. W. Burr et al., VLSI Tech. Dig. TFS1.2 (2023). 3. https://aihwkit.readthedocs.io/en/latest/pcm_inference.html#references 4. M. J. Rasch et al., AICAS (2021).