Logic Test Pattern Generation Using Linear Codes

Abstract

Logic testing of today’s integrated circuits is a task of increasing difficulty as the number of circuits or transistors packed onto a single chip grows higher and higher. Exhaustive pattern testing, with adequate partitioning of logic, has been explored regarding its potential in solving the problems in test pattern generation and fault coverage. In this paper, we propose a new method of simultaneously generating exhaustive test patterns for all possible input subsets (each corresponding to an output) up to a specified size. The method is based on the structure of linear polynomial codes and can be easily implemented by modifying existing shift-registers in an LSSD or scan path design to embody additional feedback connections. This is particularly attractive since the implementation is compatible with the approach of self-testing using pseudorandom patterns. Thus, a very reasonable strategy is to combine limited exhaustive pattern testing with pseudorandom pattern testing in cases where complete exhaustive testing is not practical. © 1984 IEEE