Publication
IEEE TC
Paper

Exhaustive Test Pattern Generation with Constant Weight Vectors

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Abstract

We develop in this paper a simple way of generating a test set which simultaneously provides exhaustive pattern testing with respect to all input subsets of a logic circuit up to a certain size. It is shown that such a test set may be formed with vectors of a particular set of weights. Main theorems and examples are established and illustrated in the binary case (for 2-value logic circuits) and then generalized to nonbinary cases (for multivalue logic circuits). Such test sets are simple in structure and become optimal in size in certain cases. It is also shown that such a test set can be effectively implemented via a scan path type shifter. Copyright © 1983 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1983

Publication

IEEE TC

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