Junction Degradation in Bipolar Transistors and the Reliability Imposed Constraints to Scaling and Design

Abstract

Stress-induced junction degradation in bipolar transistors is studied in the context of device scaling. The purpose is to define the reliability-imposed constraints on device and circuit design. The stress-induced leakage current is predominantly a Shockley-Read-Hall-like generation-recombination current. As the stress progresses, the leakage current increases, eventually reaches a maximum and then decays. The maximum leakage current is stress voltage dependent and reaches 0.26 · [exp(Vbe/2kT)− 1]pA/µm emitter edge for −5-V stress. The leakage current lowers the current gain at low biases. It affects the narrow-emitter transistors more since it is proportional to the emitter edge length. But, its impact is less significant if the transistor is operated at a higher Vbe, as required by constant-current scaling. The loss of the current gain does not affect the circuit speed directly. Instead, it reduces the logic swing and thus the noise margin of the circuit. The design to absorb the degradation with a larger initial logic swing results in a speed penalty. The reverse-stress-induced junction degradation can be eliminated by properly designing the circuit. There is no concern for emitter-coupled logic (ECL) circuits when the logic swing is less than the Vbe, of the transistors. © 1988 IEEE.