Josephson 4 K-bit cache memory design for a prototype signal processor. III. Decoding, sensing, and timing

Designs for peripheral and timing circuits for a Josephson cache memory chip, organized as 1 K × 4-bits, are described. The designs were carried out employing a 2.5-μm minimum-linewidth niobium edge-junction technology, in conjunction with the memory cell and driver array design described in the preceding companion paper. Significant changes in decoding, sensing, and timing, relating to widening operating margins over a predecessor all-Pb-alloy design are described in detail. The resultant nominal chip access time and power are, respectively, 970 ps and 10 mW.