Experimental 27 ns 1 Mb CMOS high-speed DRAM
S. Dhong, W.H. Henkels, et al.
VLSI Circuits 1989
Designs for peripheral and timing circuits for a Josephson cache memory chip, organized as 1 K × 4-bits, are described. The designs were carried out employing a 2.5-μm minimum-linewidth niobium edge-junction technology, in conjunction with the memory cell and driver array design described in the preceding companion paper. Significant changes in decoding, sensing, and timing, relating to widening operating margins over a predecessor all-Pb-alloy design are described in detail. The resultant nominal chip access time and power are, respectively, 970 ps and 10 mW.
S. Dhong, W.H. Henkels, et al.
VLSI Circuits 1989
W.H. Henkels, C.J. Kircher
IEEE Transactions on Magnetics
W.H. Henkels, N.C.-C. Lu, et al.
Workshop on Low Temperature Semiconductor Electronics 1989
L.D. Jackel, W.H. Henkels, et al.
Applied Physics Letters