Publication
VLSI-TSA 2010
Conference paper

Investigations of Cu bond structures and demonstration of a wafer-level 3D integration scheme with W TSVs

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Abstract

Evaluations of two Cu bond structures, oxide-recessed and lock-n-key, are reported. In addition to excellent electrical characteristics of bonded via chain, alignment tests show lock-n-key bond structures have better performance than oxide-recessed ones. Finally a wafer-level three-dimensional (3D) integration scheme using lock-n-key Cu bond structure with W TSV is demonstrated. © 2010 IEEE.

Date

20 Oct 2010

Publication

VLSI-TSA 2010

Authors

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