InGaAs FinFETs 3D sequentially integrated on FDSOI Si CMOS with record perfomance

Abstract

In this paper, we demonstrate InGaAs FinFETs 3D sequentially (3DS) integrated on top of a fully-depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. The low thermal budget of the top layer process caused no performance degradation of the lower level FETs. Record ION of 200 μA/μm (at IOFF =100 nA/μm and VDD =0.5 V) for 3DS integrated III-V FETs on silicon is demonstrated, with a 50% reduction of Roncompared to previous work. The achieved improved performance can be attributed to the introduction of doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.