High-Speed Split-Emitter 12L/MTL Memory Cell

Abstract

This paper describes a novel circuit/device approach that overcomes the performance drawback of the injection-sensed I2L/MTL memory cell cited in a 16-kbit static MTL RAM [7]. As a result, a compact memory cell with extremely low dc standby power in the nanowatt range and with read/write times below 5 as is achieved. This has been verified by experimental investigations on small test arrays. They have been fabricated with an advanced process featuring a p-polysilicon-base self-alignment scheme and a double-diffused p-n-p structure. In addition, computer circuit simulations have been performed that show the read delay sensitivities in large arrays. Based on these results, an access time of less than 25 ns is projected for a 16-kbit MTL RAM. Copyright © 1981 by The Institute of Electrical and Electronics Engineers, Inc.