High performance self-checking adder for VLSI processor

Abstract

The author describes a novel carry select adder design which has high performance and is self-checking without requiring a large amount of circuit overhead. A CMOS implementation of the adder is shown to comply with critical requirements of a VLSI processor. Simulation results show that the self-checking adder can easily satisfy the clock requirements of a VLSI processor. The circuit area overhead of the self-checking design is only 13% of the total adder area, which is considerably lower than that of some parity prediction checking schemes that require almost a 100% circuit overhead.