High performance low power V_T- wave-pipeline CMOS circuit in PD/SOI technology

Abstract

A Vt-wave-pipeline technique for pseudo-static CMOS circuit style was presented. The technique was evaluated by the critical path of a 64 bit carry-look-ahead adder in a 1.2 V, 0.13 μm PD/SOI technology. A performance improvement of 11.5% was achieved without significantly increasing the standby or active power. The history effect in floating-body PD/SOI technology was also found to be reduced.