Annina Riedhauser, Viacheslav Snigirev, et al.
CLEO 2023
An InGaAs-on-Si MOSFET technology platform using a CMOS-compatible fabrication flow is demonstrated. Several channel heterostructure designs are explored, with the use of thin InP barrier layers resulting in significant enhancement of mobility. MOSFETs with ft/fmax of ~350/350 GHz are demonstrated. Within the same technology platform, logic FinFET devices are also demonstrated, with record-high on-currents of 350 μA/μm. The use of S/D spacers to mitigate the parasitic bipolar effect is also explored, leading to significant reduction of off-state leakage currents. Finally, 3D sequential integration of InGaAs MOSFETs on SOI CMOS wafers is reported, showing no degradation of CMOS performance post top-level fabrication. The results indicate the strong potential for integrated InGaAs FETs towards high-performance logic and mixed-signal applications.
Annina Riedhauser, Viacheslav Snigirev, et al.
CLEO 2023
Peter Nirmalraj, Damien Thompson, et al.
Nature Materials
Svenja Mauthe, Philipp Staudinger, et al.
CLEO 2019
Éamon O'Connor, Mattia Halter, et al.
APL Materials