Hierarchical built-in self-test for system-on-chip design

Abstract

This paper describes a hierarchical built-in self-test (BIST) method for testing an integrated system chip with a global BIST controller, multiple local BIST circuits for each macro, and data/control paths to perform the system-on-chip (SoC) test operations. The global BIST controller is composed of programmable devices for storing the test patterns and programming the test commands, a state machine for executing the test sequence for each macro in an orderly manner, a dynamic random access memory (DRAM) for collecting the feedback data from the local BIST circuits, and a built-in processor for conducting intra-macro and inter-macro testing via programs from an external tester. A test algorithm is also developed for SoC design to perform self-testing and set stopping criteria in a hierarchical and parallel manner to increase fault coverage and reduce testing time. © 2005 IEEE.