Wiring for manufacturability and yield maximization in computer-aided VLSI design

Abstract

This paper presents a computer-aided wiring design methodology to provide better manufacturability for VLSI circuits. Desirable yield can be achieved by dynamically controlling the wire widths and spacings to reduce the possibility of open circuits and short circuits. On a benchmark TCM module with 124 chips, this special wiring technique completes 41,534 connections on two thin-film layers, while only 9% of the wires are potential risk sites for short circuits at minimum spacing.