Hazard-non-increasing gate-level optimization algorithms

Abstract

This paper presents hazard-non-increasing optimization algorithms. These are optimizations on gate-level logic without introduction of any further static nor dynamic hazards. Proofs are given for general theoretical results on hazard-non-increasing transformations which serve as the basis for these algorithms. The algorithms in this paper substantially augment the set of proven hazard-non-increasing optimization techniques in the literature. These algorithms are useful for hazard-free implementations of asynchronous designs.