Timing analysis in high-level synthesis

Abstract

This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network which models the data flow as well as the control flow in the behavioral input specification. The delay values for the network modules are created by invoking the same logic synthesis procedure applied after behavioral synthesis. The timing network is built only once for a given behavioral description. Several parameters are used to explore different scheduling possibilities as well as different optimization modes (area, delay), without changing the network. The use of the timing model in conjunction with a path-based scheduling algorithm is presented. Results for several benchmarks attested the accuracy of this approach.