Fundamental understanding and optimization of PBTI in nFETs with SiO ₂/HfO₂ gate stack

Abstract

An electrical measurement technique is introduced which provides direct information on the energy distribution of trapped electrons within SiO 2/HfO2 dual layer gate stacks of fully processed high-k/metal gate nFETs. Using this electron spectroscopic technique, it is shown that electron trap levels in HfO2 are located adjacent to the conduction band of Si with trap energies which agree with recently calculated defect levels induced by oxygen vacancy defects in HfO2. A strong sensitivity of these shallow defects to the gate stack processing conditions is observed and it is found that the Positive Bias Temperature Instability (PBTI) can be reduced by suppressing oxygen vacancy formation in the HfO2 layer.