Abstract
This paper describes the SRAM design concept in FinFET technologies using unique features of non-planar double-gated devices. The parameter space required to design FinFETs is explored. Variety of SRAM design techniques are presented exploiting the advantages of tied gate and independent gate controlled configurations. SRAM performance, power, and stability for FinFET devices are compared with conventional planar CMOS counterparts. Modeling the variability of FinFETs through statistics is presented as well. © 2010 IEEE.