About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IPFA 2007
Conference paper
Failure analysis of I/O with ESD protection devices in advanced CMOS technologies
Abstract
Many types of ESD protection devices such as diodes, NFETs, SCRs: and RC-triggered power clamps: having different failure mechanisms: are used in advanced CMOS technologies. Circuit schematic analysis and SEM failure analysis are utilized to clearly predict and identify the failing I/O driver/receiver devices and/or the various ESD protection devices during an ESD event. © 2007 IEEE.