Fabrication of Cu interconnects of 50 nm linewidth by electron-beam lithography and high-density plasma etching

Abstract

The feasibility of building Cu interconnects with a linewidth as small as 50 nm embedded in insulating SiO2 has been explored using the damascene process. Fine line test structures, designed for evaluating effects of small linewidth on metal line electric resistivity, were written on a poly(methylmethacrylate) resist layer and then transferred to the underlying SiO2 layer by high-density plasma etching. Using a CHF3 etching gas and an inductive power of 400 W, we were able to produce 50-nm-wide and 150-nm-deep trenches in SiO2. These trenches were then filled with a thin (5-10 nm) TaSiN or TaN liner and a thick Cu layer by the ionized physical vapor deposition technique. The field Cu was removed by a chemical-mechanical polishing process, leaving narrow damascene Cu in the oxide trenches. Direct current resistance measurements have indicated a wide distribution of resistivity in these fine lines. The low end of the distribution is close to the effective resistivity of a perfect Cu line. The high values are indicative of severe necking or other imperfections induced during the fabrication process. © 1998 American Vacuum Society.