About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
SSDM 1992
Conference paper
Fabrication and measurements of ultra-short silicon MOSFETs
Abstract
Double Al gate silicon MOSFETs have been fabricated with channel lengths ranging from 125 nm to 7.7 nm using a novel step/edge technique. The devices exhibit lateral tunneling between inversion layer source/drain extensions in the sub-threshold region and inversion layer conduction above threshold. At 0.45K and in devices shorter than 21 nm periodic oscillations are observed at bias voltages where the short-gate region is inverted. These are attributed to quantum interference arising from the ultra-short channel length. At bias voltages where the short gate region is in depletion, lateral tunneling is observed between the two inversion layer contacts. The lateral tunneling consists of a superposition of resonant tunneling peaks caused by defect states in the short channel region.