As Extreme Ultraviolet (EUV) lithography has matured, numerous imposing technical challenges have been the focus of intense scrutiny, including the EUV radiation source, reflective optics, and fundamental mask fabrication. There has been a lurking question on the state of mask defectivity that has been almost unanswerable until the recent relative maturation of the rest of the infrastructure. Without readily available actinic blank or patterned inspection systems, EUV blank and mask manufacturers must continue to rely on relatively low resolution optical systems for blank characterization. Despite best efforts, detectable defects still exist; these can be classified into three types: small defects that can be avoided through pattern-shift, medium defects that can be repaired, and large defects which must be suppressed during manufacture. To successfully intercept high-volume-manufacturing (HVM) for the 7nm node, aggressive, continued industry focus is required to ensure that these three defect types are addressed. Without actinic mask inspection, an unknown element with EUV lithography continues to be the presence of nondetected printable defects-defects that print on wafer despite being undetected during mask or blank fabrication. Another risk is that until recently, focus has been on developing techniques to identify catastrophic defects, while past manufacturing experience tells us that much more subtle defects (<10% CD variation) can have significant impact on yield and performance. Using information from many characterization sources, including blank inspections, patterned inspection, atomic-force microscopy (AFM), scanning-electron microscopy (SEM), as well as 36nm and 32nm pitch wafer printing results, we will try to address what the real current state of mask defectivity is. We will discuss techniques to answer the key questions of: "What defects print, what defects do not, and what might our inspections methods be missing?" From this vantage point, we will analyze the current mask defectivity rates and sources, and assess the gap in capability to support full HVM support.