Electrostatic discharge protection in silicon-on-insulator technology

Abstract

Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) semiconductor technology is perceived as a major roadblock for the SOI technology to become a viable mainstream contender for high-performance advanced CMOS semiconductor chips (Hu, 1994; Colinge, 1991). In this paper, our results in four successive SOI technology generations demonstrate that excellent ESD protection levels are achievable in SOI chips with no additional masking steps, process implants, costs or ESD design area. ESD results also show that the ESD robustness of the SOI ESD device is improving with partially depleted SOI MOSFET scaling from 0.25 to 0.12 μm Leff technology generations (Shahidi et al., 1999; Voldman et al., 1995, 1997, 1999). By allowing the ESD network minimum design to scale with the technology, improved ESD results are evident in each generation with no indication of any SOI-specific ESD limitations. For future technology generations below 1.5 V VDD power supply, continued improvement is anticipated due to buried-oxide scaling, lower trigger voltages, dynamic threshold voltage MOSFET (DTMOS) techniques and ESD I/O design learning (Voldman et al, 1997; Assaderaghi et al., 1994). ESD protection of partially depleted SOI technology is not a problem or technology concern using our proposed ESD methodology.