EFFICIENT FAULT SIMULATION OF CMOS CIRCUITS WITH ACCURATE MODELS.

Abstract

Large circuits are often designed by connecting together a large number of small circuits, each chosen from a library of previously designed small circuits using a given technology. Accurate models of libraries using CMOS technology, which incorporate charge sharing effects and potential hazards, are essential to evaluate the coverage of a set of test patterns and for diagnosis. Logic gate models are derived in which transistor stuck nonconducting and stuck conducting faults can be represented by stuck-at faults. Efficient gate level simulators can therefore be used to determine the fault coverage with the same accuracy that could be achieved by the slower process of switch level simulation. Previous logic gate models did not achieve this accuracy.