Over the past decades, the downscaling of transistor dimensions has improved circuit performance, power, and integration density. However, conventional device scaling is approaching the physical limits and it is increasingly difficult to sustain the same miniaturization scaling rate. Three-dimensional (3D) integrated circuits that stack multiple functional chips using through-silicon-vias (TSVs) and low-volume lead-free solder interconnects may overcome these problems, because this approach makes it possible to reduce global interconnect length and to increase device density without shrinking device dimensions. Different levels of 3D integration investigation were previously reported and updated. The current paper reviews the 3D integration technologies, including process technology and reliability characterization. © 2011 The Institute of Electrical Engineers of Japan.