Design of shifting and permutation units using LSDL circuit family

Abstract

Migration of designs into a smaller technology node, that traditionally resulted in an increase in performance, is yielding reduced returns as we scale into the sub-90nm domain. This has made it imperative to explore alternative methods like improvements in circuit design to sustain growth in performance of Integrated Circuits. The Limited Switching Dynamic Logic (LSDL) circuit family has been suggested as an efficient and high performance circuit design technique to overcome the problem of stagnating performance. In this paper, we present case studies in design of arithmetic units using LSDL selector circuits. The first unit we present is a shifter, with the added novelty that it can provide the shifted data in complemented or noncomplemented form without requiring an additional module for performing the negate operation. The second unit is a permute unit, used to line up data in media units using a single instruction, so that the media unit can operate on the data. However, existing permute units have a severe limitation in that they can move only discrete immutable bytes. Our module overcomes this by enabling extraction of any set of eight consecutive bits in a data stream, thus providing bit-level granularity in the permute operation, without altering the format of the existing permute instruction.