Design implications of single event transients in a commercial 45 nm SOI device technology

Aj Kleinosowski; Ethan H. Cannon; Jonathan A. Pellish; Phil Oldiges; Larry Wissel

doi:10.1109/TNS.2008.2005191

IEEE TNS

Paper

01 Dec 2008

Design implications of single event transients in a commercial 45 nm SOI device technology

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Abstract

This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets. © 2006 IEEE.

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