Design and technology challenges for sub-0.5 μm CMOS and bipolar

Abstract

The design and technology problems that must be solved in order to realize the potential performance of sub-0.5-μm CMOS and bipolar devices are discussed. High-field and high-current-density effects are among the most important issues. The goal is to prevent these effects from becoming problems and yet achieve performance as expected from scaling. It is seen that there are no simple solutions. It is a matter of trading off performance with process complexity and/or reliability in an optimal manner. Scaling CMOS to about 50-nm channel length appears to be quite possible. However, scaling bipolar to much below 0.25 μm requires more understanding of the device physics and major technology breakthroughs.