Design and optimization of ESD lateral NPN device in 14nm Fin FET SOI CMOS technology

Abstract

We present the development of ESD lateral NPN device in 14nm Fin FET SOI CMOS technology using body-contact and floating-body approaches. The effects of key design factors including base length, base doping, body resistance on the triggering and ESD performance of LNPN device are investigated to achieve an optimized design.