About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
ISSCC 2000
Conference paper
Delay variability: Sources, impacts and trends
Abstract
A study on the impact of environmental factors, power supply voltage and mask imperfections on the electrical performance of integrated circuits was performed. The canonical circuit composed of a source buffer driving an identical destination buffer through a length of minimum-wire width was considered. The impact of device and wire variations on the delay of the buffer/wire combination was examined. The result showed that the wire resistivity was a dominant source of delay variability and buffer insertion and wire sizing was needed to contol delay variability.