IR and thermal estimation tools, with applications to the GUTS 1 GHz processor

Abstract

Estimation for thermal effects and voltage decay across power grids in very high operating frequencies has become a crucial step in deep submicron designs. The power consumption of each circuit macro must be factored in the power grid synthesis so as to minimize potentially dangerous thermal hazards. The estimation of the voltage variation in the Vdd and ground lines across different layers of the chip's power grid guarantees the early detection of low operational voltages spots that may cause circuit malfunction. This paper presents an efficient technique to analyze the thermal and supply voltage state across the floorplan in an early stage of the design cycle. This technique is a 1st order analysis based on an "intent-based" extraction of the power grid. This is especially useful since the power grid is specified by basic geometric parameters, which can be changed to optimize the operational voltage range.