Delay measurement of experimental 2.5-μm Josephson current injection logic (CIL)

Abstract

Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10-16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10-16 J. The results are found to be in excellent agreement with estimates based on computer simulations.