Publication
IEEE Electron Device Letters
Paper

Self-Biasing Josephson Logic Circuits

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Abstract

A self-biasing network for Josephson logic circuits that permits wide variations in junction critical currents, resistors, and power supply voltage is presented. The self-biasing network automatically switches resistors in or out to make the gate currents track with the critical currents of the logic gates. Results of Monte Carlo statistical analyses of the tolerances of this scheme are presented as a function of amount of correlation between the critical currents of the logic device and the biasing network, amount of systematic variation on a chip, and number of junctions used in the biasing network. Results indicate that almost a factor of two larger variations in the critical currents of the Josephson junctions can be tolerated when the self-biasing network is used, without adverse impact on the gate delays and the power dissipation. Copyright © 1982 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1982

Publication

IEEE Electron Device Letters

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