Cycling Condition Impacts on 3D QLC NAND Reliability

Abstract

The impact of cycling conditions on data retention is evaluated using state-of-the-art 3D charge trap QLC NAND flash. We characterize the raw bit error rate and optimal read voltage offsets for different cycling parameters, such as program/erase cycle count, dwell time, and cycling temperature. The presented results can provide useful insights into the reliability of modern charge-trap NAND flash and guide the design of flash management algorithms in the NAND controller.