Publication
ESSDERC 2016
Conference paper

Complementary III-V heterostructure tunnel FETs

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Abstract

In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with Ion of a couple of μA/μm (VGS = VDS= 0.5V) combined with average subthreshold swing, SS, of 70-80mV/dec. The all III-V n-TFETs show about an order of magnitude higher Ion, but their SS is limited by the non-optimized gate stack and doping profiles. Thorough simulation studies of our devices show trap-assisted tunneling at the heterojunction to be the main limitation on SS. We will discuss the impact of different trap mechanisms and compare our results with other experimental data.

Date

Publication

ESSDERC 2016