Chip-level integration: The new frontier for microprocessor architecture

Abstract

Technology trends in recent years have led to the transition from chips containing one microprocessor core to chips containing multiple cores. This transition, first illustrated in server systems by the IBM Power4 microprocessor, is currently visible in designs ranging from dual-core desktop processors from different manufacturers, to nine cores in the recent IBM Cell microprocessor, up to over a hundred cores in various specialized systems (such as network processing or Java processing). The next step in the evolution of multi-core microprocessor architectures, which is already visible in some processor designs, consists of a more extensive integration at the chip-level, beyond the straight-forward aggregation of multiple cores on a chip. This enhanced integration is present at all levels, from the CMOS technology through processor architecture and microarchitecture, up to the on-chip system software. At the technology level, for example, the integration of embedded DRAM (eDRAM) on the same chip as the processor cores creates new design points that are different from those in SRAM-based designs. Similarly, three-dimensional integration offers the potential for becoming the successor to CMOS technology, in a similar manner as CMOS was the successor to bipolar technology, since there are similar tradeoffs in terms of power consumption, performance and density. At the processor architecture level, the integration of asymmetric cores (cores with the same instruction set architecture but different performance characteristics) and heterogeneous cores (cores with different functionality) is complemented with the integration of supporting functions that are increasing in their functionality (logic or processing cores for communications, direct memory access, data compression, security, power management, reconfigurable logic, etc.). In addition, new functionality expressed in terms of new instructions continues being architected into the processor cores. At the onchip system software level, support for specialized features such as virtualization, dynamic execution environments, power management, is becoming part of the chip architecture. These innovations are enabling the evolution of microprocessors into "application-optimized systems" by leveraging modularity at all levels, in direct correlation to the levels where the innovations are taking place. As a result, new classes of applications and systems are expected to emerge, made possible by the significant gains achieved through the chip-level integration. While there are many reasons that support the trends in the evolution of chip-level integration for microprocessors, there are also many challenges in pursuing such objectives. The current trends make ever more important the need for identifying the emerging tradeoffs in chip-level architectures, the need to determine how those tradeoffs can be investigated and evaluated, and how proposed innovations can be incorporated at the chip level. The challenges that exist in this front can be illustrated with some recent examples, yet there are still many opportunities available in this emerging area which appears ready for further innovation. The resulting chip-level multi-core (parallel) microprocessors create new challenges/opportunities in terms of their programmability as well as in terms of the parallel algorithms that are best suited for their exploitation. Traditional techniques used in the development of parallel algorithms might no longer be sufficient to leverage the increasing heterogeneity in functionality becoming available in chip-level multiprocessors.