Challenges raised by long on-chip wiring for CMOS microprocessor applications

Abstract

Rigorous three-dimensional line parameter calculation and lossy-line simulation are conducted for representative long, on-chip wiring. Measurements are carried out for 1.6 cm long lines built on 5-metal-layer structures. By using a full-wave electromagnetic analysis code, RLC transmission-line parameters are extracted. A distributed transmission line network representation is also developed to provide accurate models. Finally, representative simulations are used to compare RC-circuit representation to transmission line modelling.