Challenges facing copper-plated metallisation for silicon photovoltaics: Insights from integrated circuit technology development

Abstract

Copper-plated interconnects were widely adopted for volume manufacture of integrated circuits after more than a decade of intensive research to demonstrate that use of Cu would not impact device reliability. However, although Cu-plated metallisation promises significantly reduced costs for Si photovoltaics, its adoption in manufacturing has not gained the same traction. This review identifies some key challenges facing the introduction of Cu-plated metallisation for Si photovoltaics. These include the following: (1) increased carrier recombination due to the use of Cu for metal contact formation; (2) reduced module reliability due to adhesion or contact integrity failures; and (3) limited availability of cost-effective processes and equipment for metal plating. For integrated circuits, Cu's low electrical resistance and high resistance to electromigration provided an impetus for the large investment in process development that was required to realise Cu-plated interconnects. However, the technical advantages of using Cu for Si solar cell contacts are not as compelling, as solar cells can tolerate larger feature sizes thus reducing the criticality of the contact metal's conductivity and electromigration properties. Additionally, for Si photovoltaics, low cost is paramount, and new challenges arise from the need for modules to absorb light and operate in the field for 25+ years in diverse outdoor climates. However, with the scale of Si photovoltaic manufacturing expected to increase dramatically in the next decade, the use of large quantities of silver for cell metallisation will provide an incentive to address reliability concerns regarding the use of Cu for Si photovoltaic metallisation.