Case study of fault-tolerant architectures for 90nm CMOS crythographic cores

Abstract

This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been applied. One of the fault-tolerant architectures is a novel four-layer architecture exhibiting a large immunity to permanent as well as random failures. Characteristics of the averaging/thresholding layer are emphasized. Measurement results show advantage of four-layer architecture over triple modular redundancy in terms of reliability. © 2007 IEEE.