Carrier mobility enhancement in strained Si-On-Insulator fabricated by wafer bonding

Abstract

N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-On-Insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content, respectively) has been demonstrated in SSOI MOSFETs. This could lead to next generation device performance enhancement.