Backward compatible connectors for next generation PCIe electrical I/O

Abstract

A backward compatible PCIe connector targeting 25-32Gb/s per-channel data rates was jointly developed under a collaboration between IBM Research and Amphenol Corporation. To demonstrate the improvement on loss/reflection/crosstalk, an evaluation board with both original and new PCIe connector footprints was designed, fabricated, and tested. 3D full-wave simulations were performed and correlated with measurement results. Optimal pad and ground configurations were used to update PCIe channel budget/specifications and provide design recommendations for potential PCIe Gen5 channels.