About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
ECTC 2018
Conference paper
Backward compatible connectors for next generation PCIe electrical I/O
Abstract
A backward compatible PCIe connector targeting 25-32Gb/s per-channel data rates was jointly developed under a collaboration between IBM Research and Amphenol Corporation. To demonstrate the improvement on loss/reflection/crosstalk, an evaluation board with both original and new PCIe connector footprints was designed, fabricated, and tested. 3D full-wave simulations were performed and correlated with measurement results. Optimal pad and ground configurations were used to update PCIe channel budget/specifications and provide design recommendations for potential PCIe Gen5 channels.