Auto-assign method for large scale flip-chip package design

Abstract

The package size for Application-Specific Integrated Circuit (ASIC) becomes larger; the mainstream size is above 50mm * 50mm for current communication and networking ASICs with more than 2000 IOs. It will take more and more time to assign logical connections from chip solder bump to package solder ball across the substrate before layout design start, so an effective method of automatic assignment for package design is key for turn-around time (TAT) reduction. The benefit of package connections TAT reduction is to drive fast time to market based upon current chip-package co-design methodology. An example of real ASIC in production is presented in this paper to demonstrate the effectiveness of this automatic assign method that is integrated in so called Auto-Assign tool. © 2011 IEEE.