ATPG VIA RANDOM PATTERN SIMULATION.

Abstract

Fast hardware fault simulators may change the economics of test pattern generation. Test patterns can be generated by simulating randomly generated input patterns until one is found which detects a previously undetected fault. If simulation is sufficiently inexpensive, this method may be cheaper than running a conventional ATPG (automatic test pattern generation) program. The authors examine the work required to perform ATPG by simulation. For a sample of combinational networks, extensive fault simulations were performed. Results are presented in terms of the number of random patterns that were simulated to achieve a certain coverage, the amount of simulator work required, and the number of test patterns which were selected by the process. Heuristics were used to reduce the size of the test sets. These heuristics required only a small amount of additional simulation, but they resulted in substantial reductions in the number of test patterns.