Annealing of surface states in polycrystalline-silicon-gate capacitors

Abstract

Charge injection at the polycrystalline-silicon-SiO2 interface of phosphorus-doped, polycrystalline-silicon-gate MOS capacitors can cause excess currents during quasistatic C-V measurements and hysteresis in high-frequency C-V curves. The effect of annealing in nitrogen and forming gas at temperatures between 300 and 850 °C on these instabilities as well as on surface states Nss and surface charge Qss has been studied. To distinguish effects occurring at the substrate Si-SiO2 interface from effects occurring at the polycrystalline-silicon-SiO2 interface, measurements are also reported of the effect of annealing Si-SiO 2 structures without gate electrodes, in the same temperature range and atmospheres. There is a minimum in Nss after anneal of samples without electrodes in forming gas at 400 °C. Reaction with hydrogen is essential to anneal surface states; thermal anneal is not sufficient. Some reaction, possibly formation of SiO, occurs above 450 °C that increases Nss and may increase Qss. Anneal of polycrystalline- silicon capacitors requires temperatures high enough for hydrogen to diffuse through polycrystalline silicon but low enough that surface states are not generated. A model is discussed that correlates midgap surface states with the B2 band, an optical-absorption band in SiO2 at 5.1 eV. Charge injection at the n-polycrystalline-silicon-SiO2 interface correlates with the E1′ band in SiO2.