Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery and fluid-guiding structures improve the heat-removal performance for the nonuniform power maps of high-performance microprocessor chip stacks. Accordingly, an extension of the porous-media multi-scale modeling approach is presented as an efficient approach for designing nonuniform heat transfer cavities. A tensor description in combination with a look-up table is proposed to physically describe periodic porous media, such as pin-fin arrays, in detail. Conjugate heat and mass transfer sub-domain modeling is performed with periodic boundary conditions to derive the orientation-dependent permeability and angle offset between the pressure gradient and the Darcy velocity direction for pin-fin arrays with a pin diameter of 50 μm and pitch and height of 100 μm. A local permeability minimum at a flow direction of approx. 30° could be identified. At higher velocities, the fluid flow is biased towards the symmetry lines of the pin-fin array. The modeling concept was validated with experimental readings of a nonuniform, double-side-heated single test cavity. The main characteristics of the temperature field with respect to the four-port architecture, the guiding structures, the fluid temperature increase, and the nonuniform power dissipation are predicted correctly. A statistical comparison of power maps with different heat transfer contrast values resulted in a mean accuracy <6% at a maximal standard deviation of 22.2%. Finally, the potential of the four-port architecture for nonuniform power maps with hot spots in the corners was demonstrated. © 2011 IEEE.