Multilayer (3D) integrated circuit technology (3D chip technology) provides an attractive alternative to conventional circuit scaling methods, which rely solely on continued shrinking of device dimension. Chip stacking, through the use of through silicon vias (TSVs) and micro ball grid arrays or copper pillars, allows increasing chip complexity in a node independent way. 3D chip technology also opens up a new way to combine different chip technologies for the fabrication of advanced hybrids. The difficulties associated with 3D technology development include basic technology questions, such as thermal characteristics of chip stacks, chip design, design for test, and test methodologies. We will review results from a test site designed expressly to investigate these issues and discuss test methods used to support diagnostic test of 3D chips in a research environment.