ECCE 2020
Conference paper

An Integrated Programmable Gate Timing Control and Gate Driver Chip for A 48V-to-0.75V Active-Clamp Forward Converter Power Block

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This paper presents an integrated programmable gate timing control and primary gate driver chip for an active-clamp forward converter (ACFC) Power Block for data center applications. The ACFC Power Block converts 48 V intermediate bus voltage to processor core voltage on a motherboard with high power density. To improve the overall efficiency and reduce the system form factor, the gate timing control function and gate driver with a high voltage level shifter are integrated on a gate driver chip. These features in the gate driver chip enable the Power Block to optimize the timing of switching transistors and therefore achieve optimum efficiency. The silicon chip is fabricated in a 0.13 µm BCD process. Initial hardware operates at 48 V input and 0.75 V output voltages. Full gate timing control functions have been verified by measurement. An electrical model of this converter shows over 90% efficiency at 130 A.