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IEEE Journal of Solid-State Circuits
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An Experimental 5-Gb/s 16 x 16 Si-Bipolar Crosspoint Switch

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Abstract

An experimental 16 x 16. nonblockine asynchronous crosspoint switch with a data rate of 5-Gb/s per channel is presented. Implemented in a 0.8-μm, double-poly, self-aligned Si-bipolar ECL technology, the 3 x 3-mm<sup>2</sup> chip, featuring a multiplexer-type architecture with a three-device crosspoint cell, demonstrates a nominal data path delay of 420 ps with 12.5-ps rms jitter and a setup time of 1 ns and dissipates about 4.6 W. © 1992 IEEE

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IEEE Journal of Solid-State Circuits

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